The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Some clocked systems use, instead of a single clock signal, a quadrature clock having an in-phase (“I”) clock path and a quadrature-phase (“Q”) clock path. The signal on the Q-path is 90° out of phase with the signal on the I-path. In some differential architectures, there may be four clock paths, including not only an I-path and a Q-path, but also an inverted I-path, referred to as “Ī” (“I-bar” or “IB”), and an inverted Q-path, referred to as “Q” (“Q-bar” or “QB”).
Quadrature clocks may be used, for example, in certain transceivers for image rejection in direct conversion and low-IF architectures.
One way to generate quadrature clocks is to generate a clock signal with twice the desired frequency (using, e.g., a phase-locked loop), and then to pass that signal through a divide-by-2 circuit, which results in the two quadrature components (“I” and “Q”) at the correct frequency, each having a 50% duty cycle. Passing the inverted clock through the divider as well will also result in the two inverted quadrature components (IB and QB), again each having a 50% duty cycle.
For some applications, a 25% duty cycle may be preferred. However, previously known techniques for generating 25%-duty-cycle quadrature clock components often result in noise, as well as phase mismatch among the quadrature components.